The vast majority of integrated circuits (ICs) are synchronous circuits. In a synchronous circuit, one or more clock signals are used to synchronize data transfers between sequential elements. A data signal must be timed correctly relative to a clock edge for capturing the data signal. This is an essential requirement for sequential elements to behave correctly. At least three timing specifications may identify the requirements for ensuring reliable operation of the sequential elements, namely, a setup time, a hold time, and a minimum period duration. The setup time is the minimum time a data signal must be kept stable before a capturing clock edge. The hold time is the minimum time a data signal must be kept stable after the capturing clock edge. The minimum period duration is the minimum required length of the clock period.
Because of the importance of the clock signals for the correct behavior of the synchronous circuit, a lot of attention is given to the related implementation methods, and also the corresponding verification steps. Implementation and verification can, however, be complicated due to the impact of device routing on the distribution of signals and the statistical nature of fabrication variances. The timing behavior of a synchronous circuit may also be influenced by phenomena or conditions like, e.g., the die temperature, IR drop effects, and the operating voltage. Another complication may arise when several clock sources are allowed for the synchronous circuit in question, especially if each clock source can be arranged, e.g., programmed, to provide multiple clock frequencies to a single clock tree.
A design process for specifying a new synchronous device may be based on timing constraints, which identify requirements for a clock tree. These constraints can be evaluated by, e.g., specific electronic design automation (EDA) tools which ensure that the resulting logic and its physical implementation meet the requirements formulated in terms of constraints. Timing constraints are commonly used in synthesis tools, placement algorithms, routing of clock and data signals, and related optimizations, and in verification methods such as Static Timing Analysis (STA).
Constraints may describe, for example, frequency-related aspects of the clock behavior as well as exceptions for supporting data paths that require multiple clock cycles to complete. Determining the constraints on the basis of a specification can in many aspects be a manual effort and the correctness of the thus-determined constraints can often be ensured only by reviews. Another method for verifying timing behavior comprises gate-level simulations with timing information extracted from a physical implementation of the synchronous circuit. Such timing simulations may, however, be limited in their coverage because they may be capable of detecting an error only when an error scenario is stimulated. It may be impossible to stimulate all possible paths due to the runtime of such simulations, the amount of options, and the complexity of identifying and creating all corresponding stimuli.
Another problem which may arise is that of verifying that a given semiconductor device uses a correct clock setup. A variety of methods have been devised for this purpose. One implementation uses additional hardware elements as check elements to measure the frequency of the clock to be verified with respect to a second clock, which is assumed to have a known frequency. For this purpose, the parameters of the expected clock frequency have to be specified in relation to the known clock. This may be performed using software and may have to be adjusted whenever the clock setup changes. Any incorrect or missing programming of the check elements or any false assumption may result in failures or unreliable device behavior. On the other hand, in some cases the actual device may operate correctly, even when overclocked. The method, however, requires using parameter values that allow a safe setup using assumptions of the specification. In another method, analog delay elements are arranged on a clock path so that they prompt a certain action when a certain clock parameter is incorrect.
Thus, while there are methods for verifying the correct clock setup within a semiconductor device, only few of them are related to the set of constraints that is actually used in implementing the logic and the related clock trees. Therefore, assumptions made during physical implementation of the semiconductor design are not necessarily fulfilled. Larger discrepancies can in some cases be detected quickly by the resulting device malfunctions, while small errors in the setup may pass unnoticed. Also, the need for programming a large number of check devices may result in similar mistakes, while the absence of such programming may cause the check devices to be turned off. This may cause an unreliable behavior that can rarely be noticed. It may even cause physical damage to a device when in effect for longer duration.
There is a need for a simple, easily implementable verification structure that detects when the clock setup causes unreliable behavior.
A synchronous circuit is a circuit that comprises at least two, and typically a great number of, sequential logic elements that are synchronized, or clocked, by one or more clock signals. A logic element, e.g., a stateful element such as a latch, a flip-flop, or register, or a stateless element such as a gate, an inverter, or a multiplexor, may be referred to herein as a cell.
In a typical scenario, a launch cell outputs a data signal, e.g., a bi-level signal, in response to triggering edges of a launch clock signal applied at the launch cell. The data signal propagates to a capture cell via a data signal path. The capture cell samples the data signal in response to triggering edges of a capture clock signal which has the same clock rate, i.e., clock frequency, as the launch clock cell. Depending on the implementation, only rising edges or only falling edges are triggering edges, or both rising edges and falling edges are triggering edges.
The data signal arriving at the capture cell needs to be timed correctly relative to the capture clock signal for the capture cell to sample the data signal correctly. Typically, three timing requirements must be satisfied to ensure that the capture cell samples the data signal correctly: a setup time, a hold time, and a minimum period duration. The setup time is the minimum time before a capturing clock edge during which the data signal must be stable. The hold time is the minimum time after the capturing clock edge during which the data signal must be stable. The minimum period duration is the minimum required length of the clock period. The clock period is the duration of one clock cycle, e.g., the time from one rising edge to the next rising edge of the clock signal.
Verifying that a synchronous circuit satisfies the timing requirements for all of its components can be difficult on account of the large number of clocked components of the synchronous circuit, the statistical nature of fabrication variances, and physical parameters or effects which may have an influence on timing, such as temperature, current-resistance (IR) drop effects, and the operating voltage. Furthermore, a synchronous circuit does not necessarily comprise its own intrinsic clock source but may be arranged to receive a clock signal from an external clock. It may therefore be necessary to verify correct synchronization of the synchronous circuit for a whole range of possible clock frequencies.